The present application may relate to co-pending application Ser. No. 09/745,660, filed Dec. 21, 2000 and Ser. No. 09/745,281 filed Dec. 21, 2000, which are each hereby incorporated by reference in their entirety.
The present invention relates to a method and/or architecture for implementing phase-locked loops (PLLs) generally and, more particularly, to a method and/or architecture for implementing linearized digital PLLs.
Conventional approaches for implementing PLLs include the bang-bang approach which comprises taking snapshots of the phase error with respect to edges of incoming data. The bang-bang approach corrects on every data edge based solely on the direction (polarity) of the offset. As a result, a bang-bang system is never truly xe2x80x9clockedxe2x80x9d. In the best case, a bang-bang system is nearly locked and makes a correction at every data edge (i.e., clocks are either switched clockwise or counter clockwise depending on the polarity of the phase offset). The bang-bang approach has the disadvantage of introducing excessive jitter in the resulting recovered clock since the clock is being shrunk or expanded at every edge.
Referring to FIG. 1, a circuit 10 implementing a conventional bang-bang approach for constructing digital phase locked loops is shown. The circuit 10 involves the use of over sampling methods to determine in which quadrant of the clock the data edge resides. The quadrant information is then applied to an adjustment mechanism which moves the clock the appropriate direction at each interval. No information associated with the magnitude of phase error is retained or utilized. Polarity of the error and presence of a data transition are the only information used to adapt the phase of the clock to the incoming datastream.
Referring to FIG. 2, a flow diagram 30 illustrating the operation of the conventional bang-bang circuit 10 is shown. The circuit 10 checks for a data edge and determines the relative polarity between the data and clock. If the polarity of the data relative to the clock is positive, the clocks are switched counterclockwise. If the polarity of the data relative to the clock is negative, the clocks are switched clockwise.
Since the circuit 10 does not use magnitude information, a transfer function is exhibited at the phase detector which has the characteristics typical of a bang-bang approach. Such detectors have an inability to tolerate large input signal distortion, such as the distortion that may be found at the end of typical wired media.
The present invention concerns a method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal based on the result of step (C).
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a linearized digital PLL that may (i) reduce the sorts of distortion associated with media induced effects, (ii) reduce duty-cycle-distortion (DCD) and/or (iii) reduce data-dependant-jitter (DDJ), (DCD and DDJ may be lumped into the single category of systematic jitter).